The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs, but it has also increased the complexity of processing and manufacturing ICs.
For example, a mandrel-cut double patterning technique is generally used when fabricating IC devices with high density, such as devices with fin-like field effect transistors (FinFETs). Mandrel-cut double patterning technique typically uses two patterns. The first one defines a mandrel pattern with relatively uniform pattern pitch and sizes, and the second one defines a cut pattern. The cut pattern removes unwanted portions of the mandrel pattern, a derivative, or both. Using such technique typically improves photolithographic process window. However, current mandrel-cut double patterning techniques are not totally satisfactory. For instance, some cut pattern designs have unnecessarily complicated pattern layout and/or narrow end-to-end spaces between patterns, making it difficult for mask and wafer fabrication.
Accordingly, improvements in cut pattern designs are desired.